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February 1998
ML4621 Data Quantizer
GENERAL DESCRIPTION
The ML4621 data quantizer is a low noise, wideband monolithic IC designed specifically for signal recovery applications in fiber-optic receiver systems. It contains a two stage wideband limiting amplifier which is capable of accepting an input signal as low as 2mV with a 55dB dynamic range. This high level of sensitivity is achieved by using a DC restoration feedback loop which nulls any offset voltage produced in the limiting amplifier. The output stage is a high speed comparator circuit with both TTL and ECL outputs. An enable pin is included for added control. The minimum signal discriminator circuit provides a link monitor function with a user selectable reference voltage. This circuit monitors the peaks of the input signal and provides a logic level output indicating when the input falls below an acceptable level. This output can be used to disable the quantizer and/or drive an LED, providing a visible link status.
FEATURES
s
50MHz minimum bandwidth for data rates of up to 100MBd Can be powered by either 5V providing TTL level outputs, or -5.2V providing ECL level outputs Low noise design: 25V RMS over 50MHz noise bandwidth Adjustable link monitor function
s
s
s s s
Wide 55dB input dynamic range 10ns minimum input pulse
BLOCK DIAGRAM
(Pin Configuration Shown is for PLCC Version)
10
CF1
6 5
VIN+ VIN-
VDC
8
ee eS as le P
A1 DC AMP REF THRESHOLD GENERATOR
ew rN fo 24 46 L 2/M 62 L4 M
9 12 11 13 14
ns sig De
17
16
CF2
VOUT+
VOUT-
CMP+
CMP-
ECL+
ECL-
VCC VCC TTL
28 19
A2
ECL CMP
TTL CMP
TTL OUT
20
CMP ENABLE
3
FILTER
23
VREF
22
VTHADJ
MINIMUM SIGNAL DISCRIMINATOR
ECL LINK MON
1
TTL LINK MON
2
27
INOM
26
ISET
24
CPEAK
GND TTL
18 21
GND
1
ML4621
PIN CONFIGURATION
ML4621 24-Pin Narrow DIP (P24N)
ECL LINK MON TTL LINK MON CMP ENABLE VIN- VIN+ VDC CF2 CF1 VOUT- VOUT+ CMP+ CMP- 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC INOM ISET CPEAK VREF VTH ADJ GND TTL OUT VCC TTL GND TTL ECL+ ECL-
TOP VIEW
ML4621 28-Pin PLCC (Q28)
1 ECL LINK MON 2 TTL LINK MON 3 CMP ENABLE
27 INOM
28 VCC
VIN- VIN+ NC VDC CF2
5 6 7 8 9
26 ISET
4 NC
25 NC 24 CPEAK 23 VREF 22 VTH ADJ 21 GND 20 TTL OUT 19 VCC TTL
VOUT+ 12 CMP+ 13 CMP- 14 NC 15 ECL- 16 ECL+ 17 GND TTL 18
CF1 10 VOUT- 11
TOP VIEW
2
ML4621
PIN DESCRIPTION
PIN NAME
(Pin Number in Parenthesis is for DIP Version)
PIN NAME FUNCTION
FUNCTION
1 (1)
ECL LINK MON ECL link monitor output. Signal is low when the VIN+ and VIN- inputs exceed the minimum threshold set by a voltage on VTH ADJ. Signal is high when input signal level is below that threshold. TTL LINK MON TTL link monitor output. Same logic function as the ECL LINK MON. Capable of driving a 10mA LED indicator. This pin is normally tied to CMP ENABLE. CMP ENABLE Low voltage at this TTL input enables both the ECL and TTL outputs. A high TTL voltage disables the comparator output with ECL+ high, ECL- low, and TTL OUT high. This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8k). This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8k). An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A capacitor from this pin to ground controls the maximum bandwidth of the amplifier to accommodate lower operating frequencies. The capacitor on this pin should match the one on CF2. Negative output of the amplifier, which is normally tied to CMP-. Positive output of the amplifier, which is normally tied to CMP+. Comparator input pin. Open base configuration relies on the DC bias of the amp output to set proper DC operating voltage. Reestablish voltage if filtering is used between VOUT+ and CMP+.
14(12) CMP-
Comparator input pin. Open base configuration relies on the DC bias of the amp output to set the proper DC operating voltage. Reestablish voltage if filtering is used between VOUT- and CMP-. ECL comparator negative output. ECL comparator positive outout. Negative supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. Positive supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. TTL data output (totem pole type output stage). Negative supply. Connect to - 5.2V for ECL operation, or to source ground for TTL operation. This input sets the minimum amplitude of the input signal required to cause the link monitors to go low. A 2.5V reference with respect to GND. A capacitor from this pin to GND determines the link monitor response time. Current into an internal diode connected between this pin and GND is turned around and pulled from CPEAK. This pin is normally connected to INOM. Sets a current of approximately 125A when connected to ISET. Positive supply. Connect to source ground for ECL operation, or to 5V for TTL operation.
16(13) ECL- 17(14) ECL+ 18(15) GND TTL
2 (2)
3 (3)
19(16) VCC TTL
5 (4)
V IN -
20(17) TTL OUT 21(18) GND
6 (5)
VIN+
22(19) VTH ADJ
8 (6)
VDC
23(20) V REF 24(21) CPEAK
9 (7)
CF2
26(22) I SET
10 (8) CF1 11 (9) VOUT12 (10) VOUT+ 13 (11) CMP+
27(23) I NOM 28(24) VCC
3
ML4621
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC - GND ................................................ -0.3V to 7.0V VCC TTL - GND TTL ................................... -0.3V to 7.0V GND ............................................... -0.3V to VCC + 0.3V Junction Temperature .............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C Thermal Resistance (JA) 24 Pin Narrow PDIP ......................................... 54C/W 28 Pin PLCC ..................................................... 68C/W
OPERATING CONDITIONS
Temperature Range ....................................... 0C to 70C -5.2V Supply Range ...................................... -5.2V 5% +5V Supply Range ......................................... 5.0V 5%
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V 5%, GND = 0V, TA = Operating Temperature Range (Note 1)
SYMBOL I CC1 I CC2 IVREF VREF AV VIN VTH ADJ Range VOS EN BW VIN PW RIN tPD AMP tPD ECL tPD TTL RVTH ADJ IVOUT I CMP PARAMETER VCC Supply Current VCC Supply Current (TTL OUT Enabled) VREF Output Current Reference Voltage A1, A2 Amplifier Gain Input Signal Range External Voltage at VTH ADJ to set VTH Input Offset Input Referred Noise 3dB Bandwidth Minimum Input Pulsewidth Input Resistance Amplifier Propagation Delay Time ECL Comparator Propagation Delay Time TTL Comparator Propagation Delay Time VTH ADJ Input Resistance VOUT+, VOUT- Output Current CMP+, CMP- Leakage Current GND + 2 With 200 Load Tied to VCC - 2V TA = 25C With 200 Load Tied to VCC - 2V TA = 25C 3.90 3.11 25 VCC - 1 4.30 3.38 VIN+, VIN- From VIN+, VIN- to VOUT+, VOUT- VIN+, = 10mVP-P From CMP+, CMP- to ECL+, ECL- VIN+, = 10mVP-P From ECL+, ECL- to TTL OUT VIN+, = 10mVP-P 4 4 4 6.8 3 VDC = VREF (DC Loop Inactive) 50MHz BW 50 VIN = 5mV 2 1 3 25 65 10 8 8 8 8 CONDITIONS VCC TTL = GND TTL = VCC VCC TTL = VCC GND TTL = GND -5.0 2.40 2.55 75 1400 2.5 MIN TYP 65 70 MAX 100 110 0.5 2.65 UNITS mA mA mA V V/V mVP-P V mV V MHz ns k ns ns ns k mA A V V V
VCM CMP CMP+, CMP- Common Mode Range ECL VOH ECL VOL ECL+, ECL- Output High Voltage ECL+, ECL- Output Low Voltage
4
ML4621
ELECTRICAL CHARACTERISTICS
SYMBOL AV ECL TTL VOH TTL VOL TTL VIH TTL VIL TTL IIH TTL IIL INOM PARAMETER ECL CMP Gain TTL Output High Voltage TTL Output Low Voltage TTL Input High Voltage Level TTL Input Low Voltage Level TTL Input High Current Level TTL Input Low Current Level VIH = 2.4V VIH = 0.4V INOM = ISET -50 -1.6 125 VCC TTL = 5V, IOH = -50A VCC TTL = 5V, IOL = 2mA 2.0 0.8 50 0 2.4 0.4
(Continued)
CONDITIONS MIN TYP 100 MAX UNITS V/V V V V V A mA A
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
5
ML4621
FUNCTIONAL DESCRIPTION
AMPLIFIER The quantizer has a two stage limiting amplifier with an input common mode range of (GND + 1.8V) to (VCC - 1.5V). Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling on the input. The input DC bias voltage is set by an on-chip network at about 1.9V when it is AC coupled. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a highpass filter with a 3dB corner frequency, fL, at:
1 fL = 2 8000 C
the stability of the feedback loop. The value of this capacitor should be at least 100 times smaller than the input coupling capacitors to avoid stability problems using the ML4621. The output of the ML4621 amplifier is isolated from the comparator and made available to the user. This allows the user to add circuitry between the amplifier and the comparator for wave shaping and other signal conditioning. COMPARATOR Two types of comparators are employed in the output section of these quantizers. The high speed ECL comparator is used to provide the ECL level outputs, and in turn drives the TTL comparator. The enable pin, CMP ENABLE, is provided to control the ECL comparator. When CMP ENABLE is low the comparators function normally. When it is high it forces ECL+ high, ECL- low, and TTL OUT high. The CMP ENABLE pin can be controlled with TTL level signals when the quantizer is powered by 5V and ground. LINK MONITOR This function is implemented by the minimum signal discriminator and the threshold generator circuits. The purpose of this function is to monitor the input signal and provide a status signal indicating when the input falls below a preset voltage level. This is done by peak detecting the output of the amplifier section and comparing this level with the voltage at VTHADJ.
(1)
Two capacitors of equal value are required since the amplifier has a differential input. One of the coupling capacitors can be tied to VCC as shown in Figure 1 if the signal driving the input is single ended. The high corner frequency can also be adjusted by attaching capacitors to CF1 and CF2. The equation for adjusting this corner is:
fH = 1 2 425 C
(2)
The offset voltage within the amplifier will be present at the amplifier's output even though the input is AC coupled. This is represented by VOS in Figure 2. In order to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. An external capacitor at VDC is used to store the offset voltage. Although the value of this capacitor is noncritical, the pole it creates can affect
470 5V 4
NC
5V 3
CMP ENABLE
2
TTL LINK MON
1 28 27 26
ECL LINK MON VCC INOM ISET
0.1F 0.5F 5 6 7 8 9 10 18pF 18pF 0.001F 11 VIN- VIN+ NC VDC CF2 CF1
NC CPEAK VREF VTH ADJ GND TTL OUT
GND TTL
25 24 23 22 21 20 19 0.1F
ML4621
VOUT-
VOUT+ CMP+ CMP- ECL+ ECL- NC
VCC TTL
12 13 14 15 16 17 18
Figure 1. ML4621 Configured for 20MHz Bandwidth with TTL Output
6
ML4621
FUNCTIONAL DESCRIPTION
(Continued)
VREF
VOUT+
REF
R1 VTHADJ
VOS
THRESHOLD GENERATOR
R2
VOUT-
Figure 2.
Figure 3.
The equation which determines the droop rate of the peak detector is:
dV IISET = dt C
Since the ML4621 has a relatively low input impedance of 6.8k and is offset by one diode drop, the equation which accounts for the load and offset is:
VTH ADJ = R 2 6800 VREF + 0.7 R1
1 2 1 2
(3)
In this equation C is the peak capacitor at CPEAK. On the ML4621 the droop rate of the peak detector can be adjusted two ways: 1) By adjusting the value of the peak capacitor at CPEAK. 2) By adjusting the charge current into the peak capacitor at ISET. The charge current, IISET, can be controlled externally by connecting a resistor, REXT, between ISET and VCC. IISET will then be:
IISET = VCC - 0.7 REXT + 1700
gb gh 6800 bR + R g + R R
cb
(6)
THRESHOLD ADJUSTMENT EXAMPLE To make the link monitor trigger when the received optical power goes below 1W (-30dBm), you first need to calculate the resultant voltage at VIN+ and VIN-. If a Hewlett-Packard HFBR-24X6 fiber-optic receiver with a responsive level of 8mV/W is used, the peak-to-peak voltage would be:
1 W 8mV = 8mVP -P W
(7)
(4)
For convenience an on-chip current source of 125A is available by connecting INOM to ISET. The threshold generator level-shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between VTHADJ and VTH (the minimum peak voltage at the input which will trigger the link monitor) is:
VTHADJ = 600 VTH + 0.7
Then the link monitor should trigger at some point slightly lower than 4mV peak. Setting VTH in Equation 5 to 3mV and solving for VTHADJ yields: VTHADJ = (600 x 0.003) + 0.7 = 2.5V This is a convenient value since the reference voltage supplied by the quantizer, VREF, is 2.5V. The link monitor has about 0.4mV (peak) hysteresis built-in. More hysteresis can be induced by connecting a resistor between TTL LINK MON and VTHADJ creating a positive feedback loop. Refer to Micro Linear's Application Note 6 for more detail. (8)
b
g
(5)
The on-chip reference voltage, VREF, can be tied directly to VTHADJ to set the threshold level. This will set the minimum input signal on the ML4621 at about 3mV (peak). A lower threshold level can be set by dividing down VREF with a resistor string, as in Figure 3.
7
ML4621
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P24N 24-Pin Narrow PDIP
1.240 - 1.260 (31.49 - 32.01) 24
PIN 1 ID
0.240 - 0.270 0.295 - 0.325 (6.09 - 6.86) (7.49 - 8.26)
0.070 MIN (1.77 MIN) (4 PLACES)
1 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
Package: Q28 28-Pin PLCC
0.485 - 0.495 (12.32 - 12.57) 0.450 - 0.456 (11.43 - 11.58) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID 8 22 0.450 - 0.456 0.485 - 0.495 (11.43 - 11.58) (12.32 - 12.57) 0.300 BSC (7.62 BSC) 0.390 - 0.430 (9.90 - 10.92)
15 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28)
0.099 - 0.110 (2.51 - 2.79)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML4621CP ML4621CQ TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 24 Pin Narrow PDIP (P24N) 28 Pin PLCC (Q28)
(c) Micro Linear 1998.
is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com
2/27/98 Printed in U.S.A.
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